The present invention relates to a semiconductor circuit. More particularly, it relates to a semiconductor circuit which constitutes a drive circuit for driving the pixels of an active panel-typed is play device using a liquid crystal panel, an organic electroluminescence panel, or the like.
An STN display device is so constituted that wiping is installed in two directions, x-axis direction (first direction) and y-axis direction (direction different from the first direction), throughout its display portion. When voltage is applied in the two directions, x and y, the liquid crystal at the intersection point is driven. An active matrix display device has an active element, such as thin film transistor (TFT), for each pixel, and in the display device, these active elements are switched and driven. These display devices are known as panel-type display device, such as liquid crystal display device and organic electroluminescence (organic EL) display device. The present invention is characterized in the circuitry of a semiconductor circuit which functions as a drive circuit for producing a screen display on a display panel, applied to these types of panel-type display devices. Also, the present invention is characterized in the circuit topology of a semiconductor integrated circuit chip wherein the above circuit is integrated.
For example, an active matrix liquid crystal display device using thin film transistors as active elements has a liquid crystal layer sealed between a pair of insulating substrates for which glass plates are favorably used. In its display area, a large number of pixels are formed in matrix arrangement. Outside the display area, a semiconductor integrated circuit chip as drive circuit is mounted. The thin film transistors constituting the individual pixels are led out of the display area through outgoing lines, and connected with this semiconductor integrated circuit chip. The thin film transistors disposed in the display area are connected with the, for example, 256 output terminals of gate drivers constituting the semiconductor integrated circuit chip through 256 gate lines in the scanning direction. The thin film transistors are selected by gate signals outputted through the output terminals, and the source lines of thin film transistors connected with the selected gate lines are supplied with indicative data. Thus, a screen display is produced.
In such an active matrix liquid crystal display device, liquid crystal driving voltage (gradation voltage) is applied to pixel electrodes for red (R), green (G), and blue (B) through thin film transistors. Therefore, no cross talk occurs between pixels, and a screen display with a large number of steps of gradation without cross talk can be produced.
FIG. 25 is a block diagram illustrating an example of the constitution of the gate driver unit the present inventors previously invented. FIG. 26 is an operating waveform chart of major parts of FIG. 25. In this constitution, address signals for selecting gate lines G1, G2, G3, G4, . . . , and G256 are of eight bits, and the address signals of eight bits [0] to [7] are counted up by address counters (not shown) and then inputted. The inputted address signals of eight bits [0] to [7] are decoded into (A000) to (A255) through a decode circuit DCR, and latched into latches LT on a latch clock. The decode outputs latched in the latches LT are inputted to a high breakdown voltage unit through NOR gates NR. The range of voltage level of the latched decode output is, for example, 3V to 0V. Shift registers may be used in place of the latch circuits.
The high breakdown voltage unit comprises level conversion circuits LS and a plurality (3×256 in this case) of high breakdown voltage inverters HV. Its output terminals (gate line terminals) GTM are connected with the gate lines of the display panel, and supply gate signals G1 to G256. The level conversion circuit LS converts inputted signals of 3V to 0V into as high a voltage level as 1.6V to −14V. Each of the gate line G1, G2, G3, G4, . . . , and G256 is provided with a gate driver GDR comprising a level conversion circuit LS and three high breakdown voltage inverters HV. The NOR gate NR is a gate for turning on and off a screen display on the display panel. During a non-display period when a full selection signal is inputted, the NOR gate NR discharges the electric charges in the pixels of the display portion.
The address signals of eight bits [0] to [7] are inputted as illustrated in FIG. 26, and latched into the latches LT when a latch clock is driven high. The latched address signals are level-shifted at the high breakdown voltage unit, and supplied as gate signals G1, G2, G3, . . . to corresponding gate lines through the gate line terminals GTM.
FIG. 27 is an explanatory drawing illustrating an example of the constitution of the level conversion circuit LS in FIG. 25, and FIG. 28 is an explanatory drawing illustrating a concrete example of the level conversion circuit LS in FIG. 25. The voltage values in FIG. 27 and FIG. 28 are as follows: VCC=3V; GND=0V; DDVDH=5V; VGH=15V; and VGL=−10V. This level conversion circuit LS comprises a series circuit of three high breakdown voltage inverters HV; a common inverter V connected in parallel with the series circuit; and a series circuit of three high breakdown voltage inverters HV. Its input is the output of a latch LT.
As illustrated in FIG. 27, the ranges of output voltage of various components are as follows: the range of output voltage of the inverter V is VCC to GND; the range of output voltage of the level conversion circuit LSa in the first stage constituting the level conversion circuit LS is DDVDH to GND; the range of output voltage of the level conversion circuit LSb in the second stage is DDVDH to VGL; and the range of output voltage of the level conversion circuit LSc in the final stage is VGH to VGL.
The level conversion circuit LSa in the first stage comprises four PMOS transistors and two NMOS transistors, as illustrated in the figure. The level conversion circuit LSb in the second stage comprises two PMOS transistors and four NMOS transistors, as illustrated in the figure. The level conversion circuit LSc in the final stage comprises two PMOS transistors and two NMOS transistors, as illustrated in the figure. The level conversion circuit LSb in the second stage and the level conversion circuit LSc in the final stage are connected together through two inverters.
FIG. 29 is an explanatory drawing illustrating an example of the constitution of the latch in FIG. 25. The latch comprises six inverters V and a NAND gate ND, as illustrated in the figure, and latches the output of the decode circuit DCR on a latch clock.
FIG. 30 is an explanatory drawing illustrating an example of the constitution of the 8-bit decode circuit in FIG. 25. The decode circuit comprises inverters V which are fed with eight bits [0] to [7] of an address signal, respectively, and NAND gates ND and NOR gates NR. Thus, the decode circuit produces 256 decode outputs (A000) to (A255).
FIG. 31 is a circuit diagram illustrating an example of the gateless driver the present inventors previously invented. This gateless driver GLDR is used together with a display panel GIPNL incorporating gates. The display panel GIPNL includes gate drivers which are formed over a substrate constituting a display panel. The gate drivers are constituted by thin film transistors formed of a high current mobility semiconductor film of low-temperature polysilicon or the like. The gate driver comprises a shift register SR, a high breakdown voltage NOR gate HNR, and a high breakdown voltage inverter HV with respect to each gate line.
The gateless driver GLDR comprises level conversion circuits LS which level-convert externally inputted full selection signals of, for example, 3V to 0V, frame leading pulses, and shift register clocks into large-amplitude signals of, for example, 16V to −14V. The gateless driver outputs these level-converted signals to the lead-out terminals GTM of the display panel GIPNL.
FIG. 32 is an explanatory drawing illustrating an example of the circuit of the shift register in FIG. 31, and FIG. 33 is a waveform chart illustrating the operation of the shift register in FIG. 32. The shift register comprises six high breakdown voltage inverters HV and two high breakdown voltage NOR gates HNR, as illustrated in the figure. The shift register is fed with a frame leading pulse which was level-shifted by a level shifter LS through the input terminal INPUT, and shifts it on a shift register clock which was similarly level-shifted by a level shifter LS. Its output is applied as gate signals G1, G2, G3, G4, . . . , and G256 to respective gate lines through the high breakdown voltage NOR gates HNR, the high breakdown voltage inverters HV, and its output terminal OUTPUT.
Documents disclosing this type of prior art include Patent Document 1.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 8(1996)-106272